Distributed Computing Papers of the Week

In this work, we demonstrate that unlocking the full potential of cryogenic CMOS requires strategic transistor and interconnect-level optimizations.

We present Ripple, a CPU-GPU co-scheduler that combines model-derived GPU memory volumes with CPU completion feedback to regulate interference.

We study cluster efficiency, measured in tokens per dollar and per joule, and show how low-latency, high-bandwidth interconnects enable economical accelerators to retain their cost advantage.

In this paper, we present xDSL-CCPP, a new application-specific code generator based upon the latest MLIR and xDSL compiler technologies, for CCPP.

We derive an analytical model that predicts AFD throughput within 3% using only profiles of colocated vLLM, telling whether switching to AFD would pay off before deploying it.

We present ShardFly, which coordinates reusable transfer planning with streaming GPU execution for synchronous, in-place weight updates.

We propose the Open Inference Market (OIM), which replaces the missing asymmetry with an economic mechanism.

AMD's MI300A (CDNA3) adds new FP8 matrix instructions and 2:4 structured-sparse instructions that the predecessor, the MI250X (CDNA2), does not have. We analyze this theoretical speedup gap on AMD's MI300A (CDNA3) against the MI250X (CDNA2) by defining a new metric, capability gain.

This paper presents Token-as-a-Utility, a model-agnostic architecture integrating inference metering, service-level-aware provisioning, and inter-operator settlement.

We propose Wave Forcing (WF), which co-designs generation, training, and execution for continuous video output with multi-step denoising.

We propose a coordination architecture that decouples cross-domain trust management and privacy enforcement from underlying blockchain protocols, requiring no protocol-level modifications.

Moreover, in cross-hardware (NUMA or node) architectures, due to imbalanced communication bandwidth, frequent communication synchronization will limit overall performance. Based on these insights, we propose CHARM+, Cross-Hardware Attention with Re-Merge Multistream Mechanism.

The framework combines edge computing for fast local pro cessing with cloud computing for resource-intensive tasks and global coordina tion.

A straightforward approach is to retain more checkpoints to reduce recomputation, but their cumulative footprint can displace reusable prefixes from other sessions and cause additional cache misses. To address these problems, we present HiState, a prefix cache management system for hybrid models serving agent workloads.

Megakernels let one persistent GPU program prepare dependent operators early and execute ready tasks together. We study the benefits and costs of these capabilities by reconstructing two LLM megakernels, ThunderKittens (TK) and VDCores, as separate kernels on H100 using their original operator code.

We present LeanSparse, a serving system that reduces both decode's persistent memory use and prefill's temporary memory demand.

We present Weights That Stay, an execution design that keeps projection shards on chip for the entire serial draft walk.

We present ForgeKernel, a kernel-generation system that accumulates and reuses knowledge across runs while enabling continued evolution of kernel architectures.

The study utilizes a mathematical model of an OEW-IM where each phase is independently controlled.

This paper presents AuditFL, a contract-backed clearing layer for auditable FL in open settings.