Hardware Architecture Papers of the Week

We propose OpenRDMA, an open-source multi-path reliable RDMA transport architecture designed for GPU-friendly communication.

It is then extended to arbitrary matrix sizes, and a systematic framework is proposed for the Stratix 10 NX TBs.

Moreover, in cross-hardware (NUMA or node) architectures, due to imbalanced communication bandwidth, frequent communication synchronization will limit overall performance. Based on these insights, we propose CHARM+, Cross-Hardware Attention with Re-Merge Multistream Mechanism.

In this work, we present Phantom, an algorithm-architecture co-designed accelerator built on temporal caching.

We present Naviq, an open-source, cycle-level software simulator for FPGA SoCs, tuned to AMD Versal-class architectures.

We develop a phase analysis that quantifies how strongly mapping topology affects system performance across hardware configurations and how mapping optimization translates into latency gains. To evaluate and exploit this design space, we present Isobar, a simulation platform integrating CIM decompositions, heterogeneous execution, and resource modeling.

To address the demand for efficient ship target detection in one-bit SAR imagery, a label self-supervised ship detection training method on one-bit non-reconstructed SAR images is proposed in this paper, which enables generic deep learning models to perform detection directly in one-bit SAR images based on the chirp scaling algorithm (CSA) without signal recovery during inference.

If most memory holds model weights, little remains for the KV cache, reducing supported context length. In this paper, we propose HyPAIC, a PAIC architecture incorporating HBF to overcome these memory constraints.

This paper presents UMLoad, a system-level model-loading accelerator that decouples a framework's logical allocations from their physical page backing.

We introduce Turbo-GMM, a single-sweep fused EM kernel that completes responsibility normalization and sufficient-statistic accumulation within one traversal of the component dimension.

We present GC-MoE, an open-source FP8/FP4 MoE inference operator for NVIDIA Hopper and Blackwell GPUs that uses CUDA Green Contexts to split the device into a small communication partition and a large compute partition.

Frame-isolated execution also overlooks highly overlapping active sets and depth relationships across adjacent frames, reloading shared attributes when working sets exceed on-chip cache capacity. To address these bottlenecks, we present GSPIM, a temporal-locality-aware 4DGS accelerator for PIM-enabled edge devices.

In this paper, we introduce SCARF, a dataflow-co-designed accelerator that aligns each bottleneck with a corresponding scene-level regularity.

We design a fully unrolled, delay-commutator streaming NTT/INTT kernel, and floorplan it across the three dies of an AMD Alveo V80.

To fill this gap, we first construct a large-scale simulation-grounded dataset with 8,626 design tasks across 10 different types of analog circuits, where each task includes a textual description, labeled I/O ports, loading condition, target specifications, a testbench, and a reference netlist. Using this dataset, we present SAFTAC, a simulation-augmented fine-tuning framework that trains LLMs to generate and revise analog circuit design.

The key insight is that precision should instead denote the refinement depth of one shared expert state. Based on this insight, we present PagedMoE, which stores each expert once using a prefix-compatible tree codebook and bitplane layout.

This separation risks removing geometric structures that appear redundant under coarse metrics but are critical for precise localization, while leaving hardware-level efficiencies in the retained geometry unexploited. We present FieldRT, an algorithm-hardware co-design methodology that uses a common analysis of geometric sensitivity and data lifetime to derive both the deployment profile and its spatial realization.

This study builds a comprehensive county-level US panel dataset spanning 2010-2024, uniquely integrating individual data center building footprints and power-plant additions.